With the development of semiconductor technology, semiconductor chip area is getting smaller and smaller while the line width inside semiconductor chip is also shrinking. Therefore, semiconductor process capability is facing a growing challenge, the precision of the process and the control of process variations also became increasingly important. Among the processes for fabricating semiconductor chips, photolithography technique is one of the most important processes. Photolithography is a technological process to transfer mask patterns of a mask plate onto a wafer through a series of steps including alignment, exposure, development, etc. Therefore, the quality of the photolithography process directly affects the performance of the ultimately formed semiconductor chip.
During photolithography process, to accurately transfer a mask pattern on a mask plate onto a wafer, a key step is to align the mask plate with the wafer, that is, to calculate the position of the mask plate with respect to the wafer to meet the requirements of registration accuracy. As the feature size getting smaller and smaller, the requirement of registration accuracy and thereby the requirement of alignment accuracy also becomes more and more strict.
In current technology, there are two methods for performing photolithography alignment. One method is a through the lens (TTL) alignment technique: using a laser beam to light up an alignment mark on a mask plate and simultaneously imaging the alignment mark onto the surface of a wafer through an objective lens; then moving the wafer base station to let a reference mark on the wafer base station scan the image of the alignment mark; in the meantime, sampling the intensity of the image and finally reaching the correct alignment position when the detector receives a maximum intensity. The other method is an off-axis (OA) alignment technique: first, by using an off-axis alignment system to gauge multiple alignment marks on a wafer and reference marks on a reference plate located on a wafer base station, alignment between the wafer and the wafer base station is thus realized; then the reference marks on the wafer base station is aligned with the alignment marks on a mask plate so that the alignment between the mask plate and the wafer base station is also realized. As such, the relative position of the mask plate with respect to the wafer is determined and alignment between the mask plate and the wafer is then realized.
According to the present disclosure, at present, most of the mainstream photolithography facilities use grating diffraction. Grating diffraction refers to that, when a light beam is illuminated on a grating type alignment mark on a wafer, the beam is then diffracted and the diffracted light carries all the information about the alignment mark. The multi-level diffracted light spread out from the grating alignment mark from different angles. After using a spatial filter to filter out the zeroth-level light, the interference image of the ±n levels of the diffracted light on the reference plane is collected. As the feature size is getting smaller and smaller, an interference image of more levels of the diffracted light on the reference plane may be collected. Further, using a corresponding reference grating to scan the image along a certain direction and the signal is simultaneously detected by a photoelectric detector. After signal processing, the position of the alignment center is then determined. The position of the alignment center may be defined in the coordinate system of the wafer base station. Then, the position of the alignment center is aligned with the alignment marks on the mask plate to realize the alignment between the mask plate and the wafer.
Grating diffraction may be used in a double exposure type double patterning process. Referring to FIG. 1, a first grating 11 along the x-axis and a second grating 12 along the y-axis are formed in a substrate 1. The first grating 11 is an alignment mark for the direction along the x-axis while the second grating is an alignment mark for the direction along the y-axis. Referring to FIG. 2, a device layer (not shown) is formed on the substrate 1 and then a photoresist layer 2 is formed on the surface of the device layer. Both the first grating 11 and the second grating 12 are covered by the photoresist layer 2 and cannot be seen from the top, thus they are represented by dashed lines. Referring to FIG. 3, using grating diffraction, the first alignment center x0 along the x-axis direction is obtained based on the first grating 11 while the second alignment center y0 along the y-axis direction is obtained based on the second grating 12. Further, reference marks on a mask plate which contains a first device pattern 3 are then aligned with the first alignment center x0 and the second alignment center y0, respectively. Afterwards, the photoresist layer 2 is exposed for the first time to define the first device pattern 3. The first device pattern 3 includes a number of parallel and equally spaced first strip lines 31.
Referring to FIG. 4, reference marks on a mask plate which contains a second device pattern 4 are aligned with the first alignment center x0 and the second alignment center y0, respectively. The second device pattern 4 includes a number of second strip lines 42 parallel to the first strip lines 31. Every neighboring pair of first strip lines 31 correspond to a second strip line 42, and all the first strip lines 31 and the second strip lines 42 are arranged in a staggered way and are spaced equally. Then the photoresist layer 2 is exposed for the second time to define the first device pattern 4. Finally, the photoresist layer 2 is developed, and then the developed photoresist layer 2 is used as a mask to etch the device layer and thus form a semiconductor structure. The ultimately formed semiconductor structure includes a number of the first strip lines 31 and a number of the second strip lines 42.
However, referring to FIG. 3 and FIG. 4, during the first exposure process, the position of the first device pattern 3, with respect to the first alignment center x0, may have an overlay shift. Correspondingly during the second exposure process, the position of the second device pattern 4, with respect to the second alignment center y0, may also have an overlay shift. Therefore, as shown in FIG. 4, the distances between each second strip line 42 and the neighboring two first strip lines 31 of the second strip line 42 may not be the same, i.e. w1≠w2. As such, on one hand, the second device pattern 4 may have an overlay shift with respect to the first alignment center x0, thus the actual position of the second device pattern 4 on the substrate may also have an alignment error with respect to its intended position; on the other hand, due to the two overlay shifts, precise alignment between the first strip lines 31 and the second strip lines 42 may not be able to achieve, thus reducing the registration accuracy between the second strip lines 42 and the first strip lines 31. All of the above factors further affect subsequent semiconductor fabrication processes and the performance of the semiconductor structure containing the second strip lines 42 and the first strip lines 31.
In view of the above problems, the present disclosure provides a new alignment strategy to reduce the alignment error and improve the performance of semiconductor structures formed by a double exposure type double patterning process using grating diffraction.